1. Field of the Invention
The present invention relates to a charge pump circuit, and more particularly, to a charge pump circuit without body effects.
2. Description of the Prior Art
Please refer to FIG. 1, which is a diagram of an electrical erasable and programmable read only memory (EEPROM) 10. The EEPROM 10 has a substrate 12, a source 14, a drain 16, a floating gate 18, and a control gate 20. There is an oxide layer 24 positioned between the floating gate 18 and a channel 22 within the substrate 12, and the substrate 12 is electrically connected to a reference voltage Vbb. Generally speaking, the reference voltage Vbb is provided by a ground voltage (0 volts). If the EEPROM 10 is an n-channel metal-oxide semiconductor (NMOS) structure, the substrate is a p-doped region, and the source 14 and the drain 16 are both n-doped regions. On the contrary, if the EEPROM 10 is a p-channel metal-oxide semiconductor (PMOS) structure, the substrate is an n-doped region, and the source 14 and the drain 16 are both p-doped regions.
The principle of the EEPROM 10 is described as follows. A control voltage Vcg inputted to the control gate 20 will alter the number of electrons stored on the floating gate 18. The electrons stored on the floating gate 18 further affect the threshold voltage associated with the channel 22. Therefore, the EEPROM 10 can store two binary values according to the electrons stored on the floating gate 18. The electrons positioned within the channels are expelled to the floating gate 18 for changing the corresponding number of electrons stored on the floating gate 18. In order to make the drain 16 and the source 14 be electrically connected, the control voltage Vcg is applied to the control gate 20 for overwhelming the threshold voltage affected by the floating gate 18. If the channel 22 is established successfully, a corresponding current will flow out of the drain 16 via the channel 22. On the contrary, if the channel 22 is not established successfully, no current will exist. Therefore, the EEPROM 10 can check the establishment of the channels, that is, detect the current flowing through the source 14 and the drain 16 to determine whether a binary value xe2x80x9c1xe2x80x9d or an another binary value xe2x80x9c0xe2x80x9d is stored.
The binary value xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written into the EEPROM 10 through a programming process and an erasing process. For example, in order to program the EEPROM 10, the control voltage Vcg having 10 volts is applied to the control gate 20, a voltage Vd having 5 volts is applied to the drain 16, and a voltage Vs having 0 volts is applied to the source 14. When electrons move from the source 14 toward the drain 16, an electric field formed between the control gate 20 and the source 14 and an electric field formed between the source 14 and the drain 16 will pull electrons from the channel 22 to the floating gate 18. In order to erase the EEPROM 10, the control voltage Vcg having xe2x88x9210 volts is applied to the control gate 20, a voltage Vs having 5 volts is applied to the source 14, and the drain 16 is floating. Because the control gate 20 has a negative voltage and the source 14 has a positive voltage, the electric field formed between the control gate 20 and the source 14 will expel electrons from the floating gate 18 to the source 14. Therefore, the EEPROM 10 is erased with few electrons left on the floating gate 18.
Recently, a demand for portable electric appliances has increased. Technology related to the EEPROM 10, such as a flash memory, has been greatly researched to meet many requirements of the portable electric appliances. In order to increase the duration of using a portable electric appliance with a limited power capacity, the portable electric appliance, generally speaking, is operated under an environment providing a low operating voltage such 3.3 volts or below. As mentioned above, the programming process and erasing process individually require the control voltage Vcg with 10 volts or 10 volts inputted into the control gate 20. Therefore, the EEPROM 10 must adopt a charge pump circuit to generate the required high voltages from the low operating voltage for executing the programming process and the erasing process.
Please refer to FIG. 2, which is a diagram of a driving circuit 30 of the EEPROM 10 shown in FIG. 1. The driving circuit 30 has a memory array 32, a clock generator 34, a first charge pump circuit 36 for generating positive voltages, a second charge pump circuit 38 for generating negative voltages, and an address decoder 40. The memory array 32 has a plurality of memory cells 42 arranged in a matrix format. The address decoder 40 can select one memory cell out of the memory array 32 to be further processed. The driving circuit 30 uses the operating voltage Vdd provided by a power supply 43 to work properly. If the operating voltage has a low voltage level such as 1.8 volts, the operating voltage Vdd cannot be used for programming or erasing the memory cell 42 successfully. Therefore, the first charge pump circuit 36 is designed for generating a positive voltage (10 volts) required for programming the memory cell 42, and the second charge pump 38 is designed for generating a negative voltage (xe2x88x9210 volts) required for erasing the memory cell 42. In addition, in order to control operations of the first and second charge pump circuits 36, 38, the driving circuit 30 uses the clock generator 34 to generating a plurality of non-overlapping clock signals for driving the first and second charge pump circuits 36 correctly. The related operation is described as follows.
Please refer to FIG. 2, FIG. 3, and FIG. 4. FIG. 3 is a diagram of the first charge pump circuit 36 shown in FIG. 2, and FIG. 4 is a timing diagram of the clock signals generated by the clock generator 34 shown in FIG. 2. The first charge pump 36 has a plurality of transistors 44, 46, 48, 50, 52 and a plurality of capacitors 54, 56, 58, 60, 62. The transistors 44, 46, 48, 50, 52 are all metal-oxide semiconductor (MOS) transistors. The clock generator 34 is used for generating a first clock signal 64 to the capacitors 54, 58 and a second clock signal 66 to the capacitors 56, 60. Furthermore, a difference between a high voltage level and a corresponding low voltage level of the first and second clock signals 64, 66 is equal to the operating voltage Vdd of the first charge pump circuit 36. As shown in FIG. 4, the transistor 44 is turned on so that the operating voltage Vdd charges the capacitor 54 at time t0. Because the transistor 44 shifts the voltage transmitted through the transistor 44 by a threshold voltage Vt, the voltage of node A is Vddxe2x88x92Vt. At time t1, the first clock signal 64 has a pulse with corresponding amplitude Vdd, and the second clock signal 66 remains at a low voltage level. Therefore, the voltage of node A becomes 2Vddxe2x88x92Vt so that the transistor 46 is turned on. The voltage of node A (2Vddxe2x88x92Vt) starts charging the capacitor 56, and the voltage of node B will approach 2Vddxe2x88x922Vt. Similarly, the voltage of node C finally will approach 5Vddxe2x88x925Vt, which is greater than the operating voltage Vdd. However, substrates of the transistors 44, 46, 48, 50, 52 are commonly connected to a ground voltage (0 volts), and a voltage difference between the substrate and the source will induce a corresponding body effect. Therefore, each of the transistors 44, 46, 48, 50, 52 shift the voltage transmitted through the corresponding transistors 44, 46, 48, 50, 52 by a greater voltage difference Vt+dV. The increment dV is generated by the body effect. When the voltage levels stored by the capacitors 54, 56, 58, 60, 62 increase, the voltage difference between the substrate and the source increases. Therefore, the body effect is serious enough to greatly reduce the output voltage when the transistors 44, 46, 48, 50, 52 are turned on sequentially. To sum up, the actual output voltage of the prior art charge pump circuit is lower than the ideal value because of the induced body effects.
It is therefore a primary objective of the claimed invention to provide a charge pump circuit without body effects to solve the above mentioned problem.
Briefly, the claimed invention provides a charge pump circuit comprising a plurality of driving units cascaded in series. Each driving unit comprises an input port, an output port, a first node, a second node, a first capacitor electrically connected to the first node, a second capacitor electrically connected to the output port, a first transistor, a second transistor, and a third transistor. The first transistor comprises a substrate electrically connected to the second node, a gate electrically connected to the output port, a drain electrically connected to the input port, and a source electrically connected to the first node. The second transistor comprises a substrate electrically connected to the second node, a gate electrically connected to the first node, a drain electrically connected to the input port, and a source electrically connected to the output port. The third transistor comprises a substrate electrically connected to the second node, a gate electrically connected to the first node, a source electrically connected to the second node, and a drain electrically connected to the output port.
It is an advantage of the claimed invention that the claimed charge pump circuit can eliminate the body effect that may affect the actual output voltage, and the efficiency of raising positive or negative voltage levels according to the claimed charge pump circuit is improved without the degrading body effects.
These and other objectives of the claimed invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.